The present invention relates generally to a shared floating gate device, and more particularly, but not by way of limitation, to a shared floating gate device having a high cell density and a method of manufacture thereof.
A common floating-gate complementary metal-oxide-semiconductor (CMOS) device can function as an electrically erasable programmable read-only memory (EEPROM) device (e.g., a nonvolatile memory storing charges in a floating gate) by using the p-channel field effect transistor (pFET) to avalanche inject hot electrons into a floating gate, and the n-channel field effect transistor (nFET) to avalanche inject hot holes into the floating gate. Hot electrons are electrons in the conduction band that have higher kinetic energy than electrons at thermal equilibrium, and hot holes are holes in the valence band that have higher kinetic energy than holes at thermal equilibrium. Avalanche injection means the hot electrons or hot holes are generated primarily by an avalanche multiplication process.
However, since the conventional techniques use SiO2 as a gate insulator, the energy barrier for injecting electrons into the floating gate is about 3.1 eV and the energy barrier for injecting holes into the floating gate is about 5 eV. That is, a hot electron should have kinetic energy of about 3.1 eV and a hot hole should have kinetic energy of about 5 eV for efficient injection into a floating gate having SiO2 as gate insulator.
Moreover, conventional EEPROM cells and memory arrays employ common-floating-gate series-nFET-pFET devices could have efficient avalanche hot-electron injection in pFET and efficient avalanche hot-hole injection in nFET by using a gate dielectric insulator having low energy barrier for hot electron injection and low energy barrier for hot hole injection. However, these conventional EEPROM cells and arrays have one access transistor for every cell, which takes additional chip area and reduces cell density. Also, common-floating-gate nFET and pFET are connected in series, thereby lacking symmetry in the way the nFET and pFET operate. Further, some conventional structures have parallel connections of nFET and pFET such that these structures are denser than series connection, but still, higher cell density is desired.